? semiconductor components industries, llc, 2002 april, 2002 rev. 5 1 publication order number: mc10e411/d mc10e411 5vecl 1:9 differential pecl/necl rambus clock buffer the mc10e411 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. the mc10e411's function and performance are similar to the popular mc10e111, with the added feature of 1.2 v output swings. the output voltage swing of the e411 is larger than a standard ecl swing. the 1.2 v output swings provide a signal which can be ac coupled into rambus compatible input loads. the larger output swings are produced by lowering the v ol of the device. with the exception of the lower v ol , the e411 is identical to the mc10e111. note that the larger output swings eliminate the possibility of temperature compensated outputs, thus the e411 is only available in the 10e style of ecl. in addition, because the v ol is lower than standard ecl, the outputs cannot be terminated to 2.0 v. this data sheet provides a few termination alternatives. the e411 is specifically designed, modeled and produced with low skew as the key goal. optimal design and layout serve to minimize gatetogate skew within a device, and empirical modeling is used to determine process control limits that ensure consistent t pd distributions from lottolot. the net result is a dependable, guaranteed low skew device. to ensure that the tight skew specification is met, it is necessary that both sides of the differential output are terminated, even if only one side is being used. in most applications, all nine differential pairs will be used, and therefore, terminated. in the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on the same package side as the pair(s) being used on that side, in order to maintain minimum skew. failure to do this will result in small degradations of propagation delay (on the order of 1020 ps) of the output(s) being used which, while not being catastrophic to most designs, will mean a loss of skew margin. the mc10e411, as with most other ecl devices, can be operated from a positive v cc supply in pecl mode. this allows the e411 to be used for high performance clock distribution in +5.0 v systems. designers can take advantage of the e411's performance to distribute lowskew clocks across the backplane or the board. in a pecl environment, series or thevenin line terminations are typically used as they require no additional power supplies. for more information on using pecl, designers should refer to on semiconductor application note an1406/d. the v bb pin, an internally generated voltage supply, is available to this device only. for single-ended input conditions, the unused differential input is connected to v bb as a switching reference voltage. v bb may also rebias ac coupled inputs. when used, decouple v bb and v cc via a 0.01 f capacitor and limit current sourcing or sinking to 0.5 ma. when not used, v bb should be left open. device package shipping ordering information mc10e411fn plcc28 37 units/rail mc10e411fnr2 plcc28 500 tape & reel marking diagram a = assembly location wl = wafer lot yy = year ww = work week plcc28 fn suffix case 776 mc10e411fn awlyyww 128 http://onsemi.com
mc10e411 http://onsemi.com 2 ? 200 ps part-to-part skew ? 50 ps output-to-output skew ? differential design ? v bb output ? voltage compensated outputs ? v ee range of 4.5 to 5.5 v ? pecl mode operating range: v cc = 4.2 v to 5.7 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = 4.2 v to 5.7 v ? internal input pulldown resistors ? esd protection: > 2 kv hbm, > 200 v mm ? meets or exceeds jedec spec eia/jesd78 ic latchup test ? moisture sensitivity level 1 for additional information, refer to application note and8003/d ? flammability rating: ul94 code v0 @ 1/8o, oxygen index 28 to 34 ? transistor count = 180 devices 1 56 7891011 25 24 23 22 21 20 19 26 27 28 2 3 4 18 17 16 15 14 13 12 v ee en in v cc in v bb nc q 3 q 3 q 4 v cco q 4 q 5 q 5 pinout: 28-lead plcc (top view) q 0 q 0 q 1 v cco q 1 q 2 q 2 q 8 q 7 q 6 q 8 v cco q 7 q 6 pin description function ecl differential input pair ecl enable ecl differential outputs reference voltage output positive supply negative supply no connect pin in, in en q0, q0 q8, q8 v bb v cc , v cco v ee nc in in figure 1. logic diagram and pinout assignment q 0 q 0 q 1 q 1 q 2 q 2 q 3 q 3 q 4 q 4 q 5 q 5 q 6 q 6 q 7 q 7 q 8 q 8 v bb en warning: all v cc , v cco , and v ee pins must be externally connected to power supply to guarantee proper operation. all v cc and v cco pins are tied together on the die figure 2. logic symbol z o v cc v cc 2.4 v r l = z o v oh and v ol levels will vary slightly from specification table z o v cc v ee 300 w rambus load r s = z o figure 3. termination alternatives
mc10e411 http://onsemi.com 3 maximum ratings (note 1) symbol parameter condition 1 condition 2 rating units v cc pecl mode power supply v ee = 0 v 8 v v ee necl mode power supply v cc = 0 v 8 v v i pecl mode input voltage v ee = 0 v v i v cc 6 v v i pecl mode in ut voltage necl mode input voltage v ee 0 v v cc = 0 v v i v cc v i v ee 6 6 v v i out output current continuous surge 50 100 ma ma i bb v bb sink/source 0.5 ma ta operating temperature range 0 to +85 c t stg storage temperature range 65 to +150 c q ja thermal resistance (junction to ambient) 0 lfpm 500 lfpm 28 plcc 28 plcc 63.5 43.5 c/w c/w q jc thermal resistance (junction to case) std bd 28 plcc 22 to 26 c/w v ee pecl operating range necl operating range 4.2 to 5.7 5.7 to 4.2 v v t sol wave solder <2 to 3 sec @ 248 c 265 c 1. maximum ratings are those values beyond which device damage may occur. pecl dc characteristics v cc = 5.0 v; v ee = 0.0 v (note 2) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 55 65 55 65 55 65 ma v oh output high voltage (note 3) 3980 4070 4160 4020 4105 4190 4090 4185 4280 mv v ol output low voltage (note 3) 2580 2750 2920 2620 2785 2950 2690 2865 3040 mv v ih input high voltage (single ended) 3830 3995 4160 3870 4030 4190 3940 4110 4280 mv v il input low voltage (single ended) 3050 3285 3520 3050 3285 3520 3050 3302 3555 mv v bb output voltage reference 3.62 3.73 3.65 3.75 3.69 3.81 v v ihcmr input high voltage common mode range (differential) (note 4) 3.4 4.6 3.4 4.6 3.4 4.6 v i ih input high current 150 150 150 m a i il input low current 0.5 0.3 0.5 0.25 0.3 0.2 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 2. input and output parameters vary 1:1 with v cc . v ee can vary +0.5 v / 0.5 v. 3. outputs are terminated through a 300 ohm resistor to v ee . 4. v ihcmr min and max vary 1:1 with v cc . necl dc characteristics v cc = 0.0 v; v ee = 5.0 v (note 5) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 55 65 55 65 55 65 ma v oh output high voltage (note 6) 1020 930 840 980 895 810 910 815 720 mv v ol output low voltage (note 6) 2420 2250 2080 2380 2215 2050 2310 2135 1960 mv v ih input high voltage (single ended) 1170 1005 840 1130 970 810 1060 890 720 mv v il input low voltage (single ended) 1950 1715 1480 1950 1715 1480 1950 1698 1445 mv v bb output voltage reference 1.38 1.27 1.35 1.25 1.31 1.19 v v ihcmr input high voltage common mode range (differential) (note 7) 1.6 2.4 1.6 0.4 1.6 0.4 v i ih input high current 150 150 150 m a i il input low current 0.5 0.3 0.5 0.065 0.3 0.2 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 5. input and output parameters vary 1:1 with v cc . v ee can vary +0.5 v / 0.5 v. 6. outputs are terminated through a 300 ohm resistor to v ee . 7. v ihcmr min and max vary 1:1 with v cc .
mc10e411 http://onsemi.com 4 ac characteristics v cc = 5.0 v; v ee = 0.0 v or v ccx = 0.0 v; v ee = 5.0 v (note 8) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f max maximum toggle frequency tbd tbd tbd ghz t plh t phl propagation delay to output in (differential) (note 9) in (single-ended) (note 10) en to q 400 350 450 600 650 850 430 380 450 630 680 850 500 450 450 700 750 850 ps t s setup time (note 11) en to in 200 0 200 0 200 0 ps t h hold time (note 12) in to en 0 200 0 200 0 200 ps t r release time (note 13) en to in 300 100 300 100 300 100 ps t skew within-device skew (note 14) part-to-part skew (diff) 50 200 50 200 50 200 ps t jitter cycletocycle jitter tbd tbd tbd ps v pp minimum input swing (note 15) 250 1000 250 1000 250 1000 mv t r /t f output rise/fall time (20%80%) 275 600 275 600 275 600 ps 8. v ee can vary +0.5 v / 0.5 v. 9. the differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential output signals. 10. the single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the ou tput signal. 11. the setup time is the minimum time that en must be asserted prior to the next transition of in/in to prevent an output response greater than 75 mv to that in/in transition. 12. the hold time is the minimum time that en must remain asserted after a negative going in or a positive going in to prevent an output response greater than 75 mv to that in/in transition. 13. the release time is the minimum time that en must be deasserted prior to the next in/in transition to ensure an output response that meets the specified in to q propagation delay and output transition times. 14. the within-device skew is defined as the worst case difference between any two similar delay paths within a single device. 15. v pp (min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. the v pp (min) is ac limited for the e411 as a differential input as low as 50 mv will still produce full ecl levels at the output. figure 4. termination for output driver and device evaluation of this device (refer to application note and8020 termination of ecl logic devices) driver device receiver device qd 50 50 v tt = v cc 2.4 v v tt q d
mc10e411 http://onsemi.com 5 resource reference of application notes an1404 eclinps circuit performance at nonstandard v ih levels an1405 ecl clock distribution techniques an1406 designing with pecl (ecl at +5.0 v) an1503 eclinps i/o spice modeling kit an1504 metastability and the eclinps family an1568 interfacing between lvds and ecl an1596 eclinps lite translator elt family spice i/o model kit an1650 using wireor ties in eclinps designs an1672 the ecl translator guide and8001 odd number counters design and8002 marking and date codes and8020 termination of ecl logic devices
mc10e411 http://onsemi.com 6 package dimensions plcc28 fn suffix plastic plcc package case 77602 issue e 12.32 12.32 4.20 2.29 0.33 0.66 0.51 0.64 11.43 11.43 1.07 1.07 1.07 2 10.42 1.02 12.57 12.57 4.57 2.79 0.48 0.81 11.58 11.58 1.21 1.21 1.42 0.50 10 10.92 1.27 bsc a b c e f g h j k r u v w x y z g1 k1 min min max max inches millimeters dim notes: 1. datums l, m, and n determined where top of lead shoulder exits plastic body at mold parting line. 2. dim g1, true position to be measured at datum t, seating plane. 3. dim r and u do not include mold flash. allowable mold flash is 0.010 (0.250) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be greater than 0.037 (0.940). the dambar intrusion(s) shall not cause the h dimension to be smaller than 0.025 (0.635). 0.485 0.485 0.165 0.090 0.013 0.026 0.020 0.025 0.450 0.450 0.042 0.042 0.042 2 0.410 0.040 0.495 0.495 0.180 0.110 0.019 0.032 0.456 0.456 0.048 0.048 0.056 0.020 10 0.430 0.050 bsc n m l v w d d y brk 28 1 view s s l-m s 0.010 (0.250) n s t s l-m m 0.007 (0.180) n s t 0.004 (0.100) g1 g j c z r e a seating plane s l-m m 0.007 (0.180) n s t t b s l-m s 0.010 (0.250) n s t s l-m m 0.007 (0.180) n s t u s l-m m 0.007 (0.180) n s t z g1 x view dd s l-m m 0.007 (0.180) n s t k1 view s h k f s l-m m 0.007 (0.180) n s t
mc10e411 http://onsemi.com 7 notes
mc10e411 http://onsemi.com 8 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc10e411/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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